|
|
Type of Document Master's Thesis Author Mochocki, Bren Christopher Author's Email Address bmochock@cse.nd.edu URN etd-03042004-140126 Title Voltage Scheduling Techniques for Dynamic Voltage Scaling Processors with Practical Limitations Degree Master of Science in Computer Science and Engineering Department Computer Science and Engineering Advisory Committee
Advisor Name Title Kevin Bowyer Committee Member Surendar Chandra Committee Member Keywords
- voltage scheduling
- low power
- embedded systems
- CAD
- DVS
Date of Defense 2003-11-18 Availability unrestricted Abstract Voltage scheduling is an essential technique used to exploit the benefit of dynamic voltage scaling processors. Though extensive research exists in this area, processor limitations such as transition overhead and voltage level discretization are not included simultaneously in any research processor model to date. Algorithms that account for individual limitations are not sufficient because some complications only emerge when limitations are considered simultaneously. We present two algorithms that yield valid results given an arbitrarily large transition time overhead. The first, LPEDF, offers a simple implementation, while the second, UAEDF, accounts for all three processor limitations to further reduce energy consumption.Files
Filename Size Approximate Download Time (Hours:Minutes:Seconds)
28.8 Modem 56K Modem ISDN (64 Kb) ISDN (128 Kb) Higher-speed Access MochockiBC032004.pdf 376.99 Kb 00:01:44 00:00:53 00:00:47 00:00:23 00:00:02