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Type of Document Dissertation Author Gupta, Ajay Kumar Author's Email Address agupta@nd.edu URN etd-04142005-170358 Title High-Bandwidth, High-Dynamic Range Signal Generation Using 1-bit Digital-to-Analog Conversion Degree Doctor of Philosophy Department Electrical Engineering Advisory Committee
Advisor Name Title Jay Brockman Committee Chair Daniel Costello Committee Member Martin Haenggi Committee Member Oliver Collins Committee Member Thomas Fuja Committee Member Keywords
- spurious-free dynamic range
- multistage DAC
- inter-symbol interference
- digital-to-analog-conversion
- Viterbi algorithm
- sigma delta modulation
Date of Defense 2005-01-20 Availability mixed Abstract $SigmaDelta$ digital-to-analog conversion has as few as two output levels, providing perfect differential linearity. However, 2-level $SigmaDelta$ DAC's suffer from instability for higher order modulation. Moreover, $SigmaDelta$'s are usually useful at high oversampling ratios only. This dissertation presents a new interpretation for $SigmaDelta$ modulation which views the $SigmaDelta$ circuit as solving an optimization problem. This viewpoint shows that the $SigmaDelta$ algorithm is a naive solution and that much better solutions are feasible.
A newly-developed solution, the M-algorithm, achieves unprecedented SNDR's and SFDR's. This new algorithm extends the stable input amplitude range to realize improved SNDR's for many partially or
completely unstable modulators. Additionally, it enables useful conversion at a lower OSR (8) than prior art.
This dissertation provides hardware results for the generation of clean, high-dynamic range 1-tone and 2-tone signals over a wide range of sampling frequencies. Single-tone signals, with bands not affected by the inter-symbol interference (ISI) problem or sampling frequency-related spurs, result in an SFDR of 75 dBc in a 250 MHz bandwidth locatable anywhere in the Nyquist frequency with a sampling frequency
of 8 GS/s.
This dissertation provides a mechanism for not only measuring the extent of ISI in hardware but also for solving the ISI problem to significantly suppress harmonic distortion and spurious. Thus, output signals in a 250 MHz band around 2.625 GHz provide an SFDR of 71 dBc for both 1-tone and 2-tone inputs.
A problem with low OSR systems, even when using the M-algorithm, is that they cannot provide adequate SNDR or SFDR for most applications. This dissertation presents a new multistage DAC architecture providing
excellent performance at extremely low OSR's. Experimental measurements demonstrate an SFDR performance of 83 dBc in a 125 MHz bandwidth centered at 325 MHz while using an OSR of only 4 and an off-the-shelf DAC. The best prior art generates 68 dB at similar frequencies with 1 GS/s (albeit real-time) and employs quadrature upconversion for higher frequency signal generation.
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