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Type of Document Master's Thesis Author Thoziyoor, Shyamkumar Author's Email Address sthoziyo@nd.edu URN etd-04162004-134011 Title PIM LITE: VLSI PROTOTYPE OF A MULTITHREADED PROCESSOR-IN-MEMORY CHIP Degree Master of Science in Computer Science and Engineering Department Computer Science and Engineering Advisory Committee
Advisor Name Title Jay Brockman Committee Chair Greg Snider Committee Member Peter Kogge Committee Member Keywords
- VLSI
- processing-in-memory
- intelligent RAM
- computer architecture
- deep-submicron
- VHDL
- DRC
- clock distribution
- power distribution
Date of Defense 2004-04-07 Availability unrestricted Abstract We describe the VLSI implementation of PIM Lite, a prototype of the first multithreaded PIM chip. We give details about the RTL VHDL model, the floorplanning of the chip, design of its clock and power distribution networks and the deep-submicron DRC that was employed like antenna rule checking and minimum density rule checking. We also describe the techniques that we used to verify the RTL VHDL model and the chip layout. We present the area, timing and power results that we obtained using the chip layout. We analyze these results and discuss the inferences. We also present lessons that we have learned about VLSI design in the deep-submicron era, obtained from our experience of designing this chip in a deep-submicron process.Files
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