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Type of Document Master's Thesis Author Yoshida, Kenji URN etd-04162004-140322 Title VLSI Implementation of Algebraically-Structured Low Density Parity Check Codes Degree Master of Science in Electrical Engineering Department Electrical Engineering Advisory Committee
Advisor Name Title Daniel J. Costello Jr. Committee Chair Thomas Fuja Committee Co-Chair Jay Brockman Committee Member Keywords
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Date of Defense 2004-02-05 Availability restricted Abstract Low density parity check codes are attractive because of their excellent perfor-mance with simple iterative message-passing algorithm. However, straightforward
hardware implementation of these codes encounters troubles because of the random-
ness of the parity check matrices.
In this thesis, we focus on algebraically constructed LDPC codes, especially
quasi-cyclic LDPC codes that were first presented by Tanner. We show that the
quasi-cyclic LDPC codes can provide us with a highly parallel decoding architecture.
Furthermore, we construct an analytical model to estimate the power/area/throughput
performance of these codes. By using this model, we find that these codes are well-
suited especially for high code rate applications.
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