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Type of Document Master's Thesis Author Joshi, Vishwanath Author's Email Address vjoshi@nd.edu URN etd-04162004-163231 Title Implementation of Locos (Local Oxidation of Silicon) Isolation Scheme in IC Fabrication Degree Master of Science Department Electrical Engineering Advisory Committee
Advisor Name Title Gregory L. Snider Committee Chair Alexie Orlov Committee Member Gary H. Bernstein Committee Member Keywords
- ND music chip
- pad-driver
- silicon nitride
- LOCOS Isolation
Date of Defense 2004-04-08 Availability restricted Abstract In this thesis a method to fabricate CMOS circuits with LOCOS isolation scheme is implemented. The basic idea is to selectively grow oxide over the field oxide regions of the devices. This is done by covering the active regions of the substrate with a thin layer of silicon nitride. Silicon nitride acts as a diffusion barrier to the oxidizing species. The processing procedure is broken down into key steps namely, nitride deposition, dry etching of the nitride and nitride removal. Each step is individually studied and characterized. Suprem3 software has been used to simulate the fabrication process and find the optimal parameters for different fabrication steps. The MOSFET devices with designed threshold voltages of 1.25 V, 1.5 V and 1.75 V have been fabricated. These fabricated devices have been tested. The quantities measured and analyzed are - contact resistance,threshold voltage, transconductance and subthreshold current characteristics. TLM measurements showed the specific contact resistances for the polysilicon and p-contact to be in the order of 0.001 Ohms square cm, which is very high (3 orders of magnitude higher). The NMOS devices with designed threshold voltages of 1.5 Volts, were found to actually have threshold voltages around 1 Volt. All the devices suffered from gate leakage.Files
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