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Type of Document Dissertation Author Zhang, Jing Author's Email Address jing.jzhang1@gmail.com URN etd-12122007-153306 Title Fabrication and Performance of Submicron Gate Length GaAs-Channel MOSFETs Using InAlP Oxide as the Gate Dielectric Degree Doctor of Philosophy Department Electrical Engineering Advisory Committee
Advisor Name Title Douglas C Hall Committee Member Gregory Snider Committee Member Patrick Fay Committee Member Thomas H Kosel Committee Member Keywords
- GaAs
- MOSFET
- InAlP
- oxide
- submicron
Date of Defense 2007-12-06 Availability restricted Abstract The prospects for developing GaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) using the wet thermal oxide of InAlP as the gate dielectric have been investigated. The microstructural properties of InAlP oxide have been examined, and the mechanisms governing the oxidation of InAlP have been explored. Fabrication processes for realizing GaAs-channel MOSFETs with sub-micron gate lengths have been developed and used to demonstrate depletion-mode transistors.The InAlP oxide is found to be largely amorphous, but contains small microcrystalline regions. Energy dispersive X-ray spectroscopic analysis shows that the oxide is composed of all pre-existing elements (In, Al, P) in addition to O. A layer of In-rich particles was observed at the oxide-semiconductor interface for thick oxides (thicknesses greater than 17 nm), but is absent in thin “device-scale” oxides. Through the use of a diffusion marker experiment it has been demonstrated that the inward diffusion of oxygen dominates the kinetics of oxide growth. This Si-like diffusion mechanism is a
Jing Zhang
critical advantage, significant because it can lead to a cleaner oxide-semiconductor interface since surface impurities remain on the outer oxide surface.
GaAs-channel MOSFETs using InAlP oxide as the gate dielectric have been fabricated and characterized. New fabrication process flows for submicron gate-length MOSFETs were developed and demonstrated. A non-self-aligned process in which the gate electrode metallization and gate oxidation region are aligned using electron-beam lithography is demonstrated for sub-micron gate lengths. An enhanced process in which the gate metallization and oxidation region are self-aligned has also been developed and demonstrated. These process improvements have enabled significant improvements in device performance over previous reports. A record peak extrinsic transconductance of 144 mS/mm and a record cutoff frequency, ft, of 31 GHz for a GaAs-channel MOSFET has been measured on self-aligned MOSFETs with 0.25 µm gate length.
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